An embodiment relates to a voltage generation circuit and, more particularly, to a voltage generation circuit which is capable of preventing unnecessary current consumption and speeding up the operating speed by controlling a clock frequency upon operation, and a nonvolatile memory device including the same.
In a nonvolatile memory device (in particular, a flash memory device that can be electrically erased and programmed), when an erase operation for erasing data stored in a memory cell and a program operation for storing data in a memory cell are performed, Fowler-Nordheim (F-N) tunneling and a hot electron injection method are used.
A flash memory device operating at a relatively low power source voltage generally includes a voltage supply circuit configured to generate a high voltage within a chip. The voltage supply circuit is configured to pump an input low voltage to a high voltage using a voltage pump circuit and output a pumped voltage.
FIG. 1 shows the voltage supply circuit of a nonvolatile memory device.
Referring to FIG. 1, the voltage supply circuit 100 includes a clock unit 110, a high voltage switch 120, and a high voltage pump 130. The voltage supply circuit 100 further includes a first comparator COM1, a NAND gate NA1, first to fourth inverters IN1 to IN4, an NMOS transistor N1, first and second resistors R1 and R2, and a capacitor C.
The clock unit 110 generates a clock in response to a clock enable signal CLK_EN. The clock generated by the clock unit 110 is input to the high voltage switch 120.
The high voltage switch 120 outputs a selection signal SEL in response to a switch enable signal SWITCH_EN and the clock generated by the clock unit 110. The selection signal SEL is input to the gate of the NMOS transistor N1.
The first comparator COM1 compares a reference voltage REF and a comparison voltage Vcomp. When the comparison voltage Vcomp is higher than the reference voltage REF, the first comparator COM1 outputs a logic low signal. When the comparison voltage Vcomp is lower than the reference voltage REF, the first comparator COM1 outputs a logic high signal.
The NAND gate NA1 performs a NAND logic combination of the clock of the clock unit 110, a pump enable signal PUMP_EN, and the output signal of the first comparator COM1 and outputs a NAND logic combination result. In the NAND logic combination, when all the input signals are at a logic high level, a logic low signal is output. When any one of the input signals is at a logic low level, a logic high signal is output.
The output signal of the NAND gate NA1 is input to the first inverter IN1. The first to third inverters IN1 to IN3 are coupled in series between the output terminal of the NAND gate NA1 and the high voltage pump 130. Accordingly, the output signal of the NAND gate NA1 is inverted and delayed by the first to third inverters IN1 to IN3 and then input to one input terminal of the high voltage pump 130.
The first and fourth inverters IN1 and IN4 are coupled in series between the output terminal of the NAND gate NA1 and the other input terminal of the high voltage pump 130. Accordingly, the output signal of the NAND gate NA1 is delayed by the first and fourth inverters IN1 and IN4 and then input to the high voltage pump 130.
The high voltage pump 130 generates a high voltage in response to the signals output from the third inverter IN3 and the fourth inverter N4 and configured to have opposite phases. The high voltage output from the high voltage pump 130 is input to a high voltage input terminal HVIN.
The first and second resistors R1 and R2 are coupled in series between the high voltage input terminal HVIN and a ground node. The comparison voltage Vcomp, output from a node of the first and second resistors R1 and R2, is input to the first comparator COM1.
The NMOS transistor N1 is coupled between the high voltage input terminal HVIN and a high voltage output terminal HVOUT. The selection signal SEL output from the high voltage switch 120 is input to the gate of the NMOS transistor N1.
The capacitor C is coupled between the high voltage output terminal HVOUT and a ground node and is charged with an output voltage output as a high voltage.
In the above-described voltage generation circuit, only when the high voltage switch 120 is driven to output the selection signal SEL of a logic high level, a high voltage output from the high voltage pump 130 is sent to the high voltage output terminal HVOUT.
In this case, in the state in which the switch enable signal SWITCH_EN is input, the high voltage switch 120 outputs the selection signal SEL in response to the clock output from the clock unit 110. Accordingly, when the clock output from the clock unit 110 has a high frequency, the operating speed of the high voltage switch 120 becomes relatively fast, resulting in an increased operating current.
However, when the clock has a relatively low frequency, the operating speed of the high voltage switch 120 becomes relatively slow, resulting in a reduced operating current.